As portable electronic devices, like cellular phones, camcorders, and game machines, have become popular, the need for embedded memory logic (EML) semiconductor devices has increased. EML semiconductor devices generally employ DRAMs as memories for high-speed operations as well as other types of circuits for other purposes.
FIG. 1 is a cross-sectional view for illustrating a method of fabricating a capacitor associated with a transistor of a typical DRAM semiconductor device. A first interlayer dielectric layer (ILD) can be formed on the semiconductor device 10. Thereafter, the first ILD can be patterned to form a first interlayer dielectric layer pattern (ILD pattern) 20 with a first opening 25 exposing the semiconductor device 10. A conductive contact plug 30 can be formed in the first opening 25 to connect to the semiconductor substrate 10.
A second ILD can be formed on an entire surface of the semiconductor substrate including the contact plug 30. The second ILD can be patterned to form a second ILD pattern 40 with a second opening 45 exposing a top surface of the contact plug 30.
A lower electrode layer and a sacrificial layer (not shown) can be conformally deposited on an entire surface of the semiconductor substrate including the second ILD pattern 40. The sacrificial layer and the lower electrode layer can be etched to expose a top surface of the second ILD pattern 40, thereby forming a lower electrode 50 and a sacrificial layer pattern, which sequentially fill the second opening 45. The sacrificial layer pattern can be removed to expose an inner wall of the lower electrode 50.
A dielectric layer 60 and an upper electrode layer can be sequentially formed on an entire surface of the semiconductor substrate including the exposed lower electrode 50. The upper electrode layer can be patterned to expose a top surface of the dielectric layer 60, thereby forming an upper electrode 70, which can fill the second opening 45 and extend outside the second opening 45 onto the top surface of the dielectric layer 60.
Fabrication of a DRAM capacitor according to the foregoing conventional method includes performing photolithographic and etching processes three times: 1) form the first opening 25; 2) forming the second opening 45; and 3) forming the upper electrode 70.
A DRAM cell capacitor can typically include a lower electrode having a height h1 of about 10000 Å, or more, to increase the integration level of the devices and provide sufficient capacitance. However, because of the height h1 of the lower electrode 50, some processes of fabricating DRAMs may not be compatible with those of logic circuits. These incompatibilities may make it difficult to simplify the fabrication of EML semiconductor devices, which may not reduce fabrication costs.